Computational Science Technical Note CSTN-202

CSTN Home

PCI Extension Bus Scalability for Multi-GPU Systems

K. A. Hawick and D. P Playne

Archived: 2012

Abstract

Graphical Processing Units (GPUs) are generally connected to their hosting processors via a Peripheral Component Interconnect Express (PCIe) bus and usually motherboards will support at most four PCIe devices. Although known as a bus, the PCIe standard is actually structured as point-to-point serial links with dynamic bandwidth negotiation. We construct a synthetic benchmark application to measure the bandwith, latency and PCIe bus contention issues that arise as a multi-threaded CPU host program delegates work to multiple GPU accelerator devices. We explore performance properties of different models of GPUs as well as that of PCIe extender cards and device chassis that support operation of more than four GPU devices from one CPU. In addition to benchmark data we discuss applications and appropriate software and threading architectures to make good use of GPUs and GPU-accelerated clusters configured in this manner.

Keywords: PCIe Bus; bus scalability; bus contention; multiple devices; GPUs; CUDA

Full Document Text: Not yet available.

Citation Information: BiBTeX database for CSTN Notes.

BiBTeX reference:

@TECHREPORT{CSTN-202,
        author = {K. A. Hawick and D. P Playne},
        title = {PCI Extension Bus Scalability for Multi-GPU Systems},
        institution = {Computer Science, Massey University},
        year = {2012},
        number = {CSTN-202},
        month = {July},
        keywords = {PCIe Bus; bus scalability; bus contention; multiple devices; GPUs;
                CUDA},
        owner = {kahawick},
        timestamp = {2012.07.02}
}


[ CSTN Index | CSTN BiBTeX ]