Computational Science Technical Note CSTN-186

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Performance of Instruction Level Parallelism on ARM Processors: Historical Measurements and Future Potential

Martin J, Johnson and K. A. Hawick

Archived: 2013

Abstract

Parallel computing at all levels is becoming important in all devices and not least in mobile and embedded systems. Many wireless, mobile and deployable devices make use of the ARM CPU and its variants. We report on investigations into measuring instruction level parallelism on the ARM processor and on characterising the fine grained parallelism of four generations of ARM cores. We discuss the implications for future applications that use such devices with parallelism and for the future of mobile computing device architectures.

Keywords: ARM CPU; multi core; instruction level parallelism; IPC; mobile devices; performance

Full Document Text: Not yet available.

Citation Information: BiBTeX database for CSTN Notes.

BiBTeX reference:

@TECHREPORT{CSTN-186,
        author = {Martin J, Johnson and K. A. Hawick},
        title = {Performance of Instruction Level Parallelism on ARM Processors: Historical
                Measurements and Future Potential},
        institution = {Computer Science, Massey University, Auckland, New Zealand},
        year = {2013},
        number = {CSTN-186},
        note = {Submitted to Parallel Computing, April 2013},
        booktitle = {Proc. 11th International Conference on Software Engineering Research
                and Practice (SERP'13)},
        keywords = {ARM CPU; multi core; instruction level parallelism; IPC; mobile devices;
                performance},
        owner = {kahawick},
        timestamp = {2013.05.18}
}


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